TMP401
SBOS371A AUGUST 2006 REVISED OCTOBER 2007
www.ti.com
16
SCL
SDA
t
(LOW)
t
R
t
F
t
(HDSTA)
t
(HDSTA)
t
(HDDAT)
t
(BUF)
t
(SUDAT)
t
(HIGH)
t
(SUSTA)
t
(SUSTO)
P
S
S
P
Figure 13. Two-Wire Timing Diagram
Table 11. Timing Diagram Definitions for Figure 13
PARAMETER
MIN
MAX
MIN
MAX
UNITS
SCL Operating Frequency
f
(SCL)
0.001
0.4
0.001
3.4
MHz
Bus Free Time Between STOP and START Condition
t
(BUF)
600
160
ns
Hold time after repeated START condition.
After this period, the first clock is generated.
t
(HDST A)
100
100
ns
Repeated START Condition Setup Time
t
(SUST A)
100
100
ns
STOP Condition Setup Time
t
(SUSTO)
100
100
ns
Data Hold Time
t
(HDDAT)
0
0
ns
Data Setup Time
t
(SUDAT)
100
10
ns
SCL Clock LOW Period
t
(LOW)
1300
160
ns
SCL Clock HIGH Period
t
(HIGH)
600
60
ns
Clock/Data Fall Time
t
F
300
160
ns
Clock/Data Rise Time
for SCL d 100kHz
t
R
t
R
300
1000
160
ns
Frame 1 TwoWire Slave Address Byte
Frame 2 Pointer Register Byte
Frame 4 Data Byte 2
1
Start By
Master
ACK By
TMP401
ACK By
TMP401
ACK By
TMP401
Stop By
Master
1
9
1
1
D7 D6 D5 D4 D3 D2 D1 D0
9
Frame 3 Data Byte 1
ACK By
TMP401
1
D7
SDA
(Continued)
SCL
(Continued)
D6 D5 D4 D3 D2 D1 D0
9
9
SDA
SCL
0
0
1
1
0
0 R/W
P7 P6 P5 P4 P3 P2 P1 P0
&
&
Figure 14. Two-Wire Timing Diagram for Write Word Format
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